Programmable memories have been implemented using non-volatile memory (NVM) cells. These NVM systems can be implemented as stand-alone memory integrated circuits or can be embedded within other integrated circuits. NVM systems have utilized a variety of cell structures for NVM cells, including floating gate cells and split-gate cells. Further, a variety of techniques have been used to perform read, program, and erase operations for NVM cells, including Fowler-Nordheim (FN) tunneling techniques. The performance of NVM cells can degrade, however, due to a variety of factors.
Program/erase performance for NVM cells, for example, is temperature dependent. In particular, the speed of program operations is slower at higher temperature than that at lower temperature. Fowler-Nordheim (FN) tunneling erase operations are faster at high temperature than that at lower temperature. These temperature variations are natural behaviors based on physical properties. These temperature dependent behaviors can lead to performance degradation. For example, a voltage ramp is often used in FN erase and soft-program operations. For the slow erase operations at lower temperatures, the time needed for the erase operation can run over the voltage ramp timing, thereby leading to dramatically degraded cycling performance.
Program/erase performance for NVM cells will also degrade dramatically after a certain number of program/erase cycles because of the accumulation of the damage due to cycling. For example, for NVM cells that utilize floating gates and tunneling oxides, more and more charges (e.g., holes and electrons) are trapped within tunnel oxide as cycle count increases, thereby damaging the tunnel oxide. This damage not only degrades program/erase performance, but it also degrades other reliability aspects for the NVM cells due to large de-trapping effects. Some of these reliability aspects include data retention bake (DRB) reliability, operating life (OL), program disturb, read disturb, and other reliability aspects for the NVM cells.
Performance degradations for the NVM cells, such as performance degradations due to temperature variations or high cycle counts, can reduce the useful lifetime for the NVM systems and integrated circuits within which these NVM systems are embedded.